Keynote: Collaborative development of quantum computer
systems - the QSOLID project

Northrop Grumman has developed a process to fabricate Josephson digital integrated circuits based on the Reciprocal Quantum Logic (RQL) gates. The chips have 13 niobium layers: 10 wiring layers (with 0.25-µm feature size) plus 3 ground plane layers. To maintain high quality, the first 10 Nb layers are embedded in a silicon-rich nitride that is deposited at high temperature. After the Josephson junctions are formed, the last 3 layers of insulator are deposited at 150°C. Shift registers were fabricated to measure process yields with recent 2,700-bit shift registers, containing 43,200 junctions each, demonstrating better than 50% yield of working circuits. The best result had 1.5 million junctions working at 1 GHz in 93,872 total shift register bits on a 10-mm x 10-mm chip. Test capabilities include 4 Kelvin wafer probing and multiple closed cycle refrigerators that each hold 16 packaged chips that have measured thousands of chips per year. Process development has not only adapted methodologies from CMOS to superconducting electronics (SCE), but also created new techniques to observe superconducting-specific properties. By incrementally increasing performance, NGSC has and is continuing to mature a SCE process while matching it with both design and test capabilities that enable beyond-CMOS capabilities, taking SCE from the exhibition of hero devices to a higher standard of performance.

In this work, we present recent progress on the semi-damascene integration to fabricate NbTiN based two-metal level αSi/NbTiN based Josephson junctions (JJs), NbTiN/HZO/NbTiN tunable Metal-Insulator-Metal (MIM) capacitors and NbTiN BEOL interconnects, that are the key building blocks for scalable Superconducting Digital (SCD) technology. Morphological characterization shows the fabricated devices are high-quality with critical dimensions (CDs) down to 50 nm. Room and cryogenic electrical measurements demonstrate amorphous Si (αSi) based JJs have Jc> 2 mΑ/µm2, with a IcRn of ~1.1 mV. The HZO MIM capacitors are tunable at high frequency upto 4 GHz with high specific capacitance Cf of 28 fF/µm2 and k-value of 30, and NbTiN BEOL interconnects have critical temperature Tc >14.5 K and high critical current density Jc >120 mΑ/µm2. The devices were fabricated on 300 mm wafers with temperature budget of 420 oC using tools and processes compatible with standard CMOS technology, providing groundwork towards enabling industrial fabrication of high-density digital stacks for high-speed and energy-efficient computing.

Superconducting digital logic is a beyond-CMOS alternative due to its high computational efficiency, small form factor and ultra-low power consumption. Superconducting NbTiN material compares favorably to earlier Nb and NbN due to higher critical temperature (Tc), higher thermal stability, and lower degradation risk during fabrication processing. Here we summarize our recent NbTiN material and process characterization for integrated circuit interconnects. Different NbTiN depositions via co-sputtering of Nb and Ti target or sputtering of a single NbTi target, and different film thicknesses of 7-200nm were deposited on 300mm Si wafers. Unpatterned films were characterized at room temperature with XRD, XRR, AFM, and sheet resistance measurements; and at cryo temperature with measurement of Tc, critical current density (Jc), and London penetration depth. Patterned structures including lines, meanders, and hall bars, with critical dimension down to 50nm were fabricated using 193nm immersion lithography and reactive ion etching (RIE) on the imec pilot line. We show how film properties including roughness of 0.2-3.9nm, room temperature resistivity of 100-460 µΩcm, and varied ratios of (111) and (200) crystal phases affect the superconducting performance of the patterned structures, which exhibit Tc up to 15K and Jc up to 120 mA/µm2.

The adiabatic quantum-flux-parametron (AQFP) [1] is an ac-biased logic family known for its ultra-low switching energy of approximately 1.4 zJ per Josephson junction (JJ) at 5 GHz, making it a promising alternative to CMOS technology. However, the scalability of AQFP circuits is constrained by the large footprint of the transformer within AQFP cells and the limitations of AC clocking [2]. The Double Gate Process (DGP) [3] is a double-active-layer niobium fabrication process which provides the opportunity to construct more compact circuit designs without the need to alter established and verified cell layouts. We present AQFP logic circuits fabricated on both active layers of the DGP and present experimental results on their operating margins.

References
1. N. Takeuchi et al., SUST 26, no. 3, 035010 (2013).
2. S. K. Tolpygo, IEEE TAS 33, no. 2, 3230373 (2023)
3. T. Ando et al., SUST 30, no. 7, 075003 (2017).

Fabrication and electrical characterization of Nb/TaNx/Nb Josephson junctions is reported. At the thickness of TaNx layer of about 10 nm, the junctions are self-shunted and display the critical current density, jc, above 100 kA/cm2, and the critical voltage, Vc, of about 0.59 mV at 4.2 K. The critical voltage is defined as Vc=IcRq, where Ic is the Josephson critical current and Rq is the resistance of the quasiparticle branch of the current-voltage characteristic (IVC) at the level of maximum Ic. The value of Rq may be different from the junction’s normal state resistance, Rn, and from the resistance obtained by a linear fit of the resistive subgap portion of the IVC. It is suggested that the junctions are promising for applications in superconducting electronics including single-flux quantum digital and quantum computing circuits.

The author received support from the NSF DISCoVER Expedition award under grant no. CCF- 2124453. The author acknowledges the use of facilities of the Materials Research Center at Northwestern University, supervised by J. B. Ketterson and supported by NSF.

Increasing the integration scale and operating speed of superconductor digital circuits requires increasing the critical current density, Jc of Josephson junctions (JJs) and reducing their area. In the current SFQ5ee process at MIT Lincoln Laboratory (MIT LL), externally shunted Nb/Al-AlOx/Nb JJs are used. The area occupied by the JJs can be reduced by 10x by implementing self-shunted junctions not requiring shunt resistors. For Nb/Al-AlOx/Nb JJs, the sufficient self-shunting occurs at Jc ~600 µA/µm2. Therefore, the next node of the superconductor electronics fabrication process at MIT LL targets JJs with Jc= 600 µA/µm^2 and the minimum JJs diameter of 0.35 µm, a 2x reduction in comparison to the SFQ5ee node. We will present data on the fabrication and properties of the self-shunted junctions, their on-chip and across-wafer uniformity, and wafer-to-wafer Jc repeatability. SNS-type JJs could be a potential alternative to high-Jc, tunnel-barrier-based JJs, where N is a highly disordered, high-resistivity “poor” metal or a heavily doped semiconductor. We have been developing JJs using nonsuperconducting NbNx (x>1) barriers and stoichiometric NbN, or Nb, electrodes. We present fabrication details and electrical properties of Nb/NbNx/Nb and NbN/NbNx/Nb junctions, in a range of barrier thicknesses from 5 nm to 20 nm, deposited by reactive sputtering and incorporated in a fully planarized multilayered process, and provide comparison to the properties of Nb/Al-AlOx/Nb junctions.

We have developed the "SIMIT Nb03P" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process. The standard fabrication process with 12 mask levels has 5 metal layers including 4 niobium superconducting layers and a Mo resistor layer. The influences of deposition parameters on film stress, electrical properties and surface roughness were studied systematically by an optical film-stress mapping system, a Physical Property Measurement System (PPMS) system, and an Atomic Force Microscope (AFM). As a result, high quality Nb, Al, Mo and SiO2 films were successfully obtained for the subsequent fabrication. The circuit fabrication starts with fabrication of Mo resistors with a target sheet resistance Rsh of 2 ohm, followed by deposition of Nb/Al-AlOx/Nb Joseohson-junction trilayer with a target critical current density Jc of 6 kA/cm2. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. Up to now, several small-scale circuits have been fabricated and successfully tested at low frequencies. The typical experimental operating margins for the bias current were found to be similar to “SIMIT Nb03” process. As a result, it is demonstrated that the superconducting large scaleintegrated digital circuits can be produced using our innovative technique, "SIMIT Nb03P."

We present the world's first implementation of a complete set of qubit control and readout functions using superconducting single flux quantum (SFQ) circuits. Our SFQ chips are integrated with qubit chips at the same temperature stage of a dilution refrigerator, addressing a major roadblock in scaling quantum computers to practical applications. This integration allows us to bypass the challenges of generating qubit control and readout signals at room-temperature and transmitting them to qubits over meters of coaxial cables. SEEQC implemented the X/Y, Z-controls integrated with digital routers and digital readout of transmons using energy-efficient RSFQ (ERSFQ) circuits. With an SFQ pulse-train-based X/Y control, we achieved single qubit gates with an average Clifford fidelity of 99.6%, the highest value to date with this approach. For the first time, we have implemented Z-control by generating the baseband flux bias waveforms with ERSFQ circuits. We demonstrated controllable two-qubit gates without any predistortion while eliminating the flux crosstalk across qubit chip. Finally, we implemented fast, high fidelity on-chip digital readout of transmons using the Josephson Digital Phase Detector (JDPD) integrated with an SFQ comparator. By applying flux bias, the JDPD evolves from a single- to double-well potential to discriminate between two phases of a readout GHz tone reflecting the qubit state. The JDPD output is then converted to a digital form with the SFQ comparator.

Hybrid superconductor–semiconductor (S–Sm) junctions are vital building blocks for next-generation quantum processors, offering stability, reproducibility, scalability, and electrostatic control. This talk presents voltage-tunable S–Sm devices integrated with Nb superconducting electronics, where split-gate-induced electrostatic fields enable nanoscale switching of conductance. We demonstrate the experimental realization of large-scale, gate-controllable field-effect quantum chips and introduce superconducting quantum point contact transistors (SQPC) arrays fabricated using split-gate technology. Emphasis will be placed on the switching properties and microwave spectroscopy of these hybrid devices, highlighting their relevance for scalable, addressable, power-efficient cryogenic electronic quantum circuit architectures.

In 1982, Fredkin and Toffoli introduced conservative logic, whereby they observed that “it is ideally possible to build sequential circuits with zero internal power dissipation.” They introduced a Switch gate which, with its inverse, constitutes a universal set of gates. We propose a dual-rail computing architecture wherein reciprocal pairs of magnetic ballistic solitons are routed on long Josephson junctions. Asynchronous Switch and Merge (Switch’s inverse) can be implemented by coupling long junctions. These two primitive gates can be combined to synthesize reversible gates such as CNOT, Fredkin, or Toffoli gates, or irreversible gates like AND and OR. Data pulses travel ballistically, powered only by their own kinetic energy. Gates are mostly elastic, so energy dissipation is very low. Dissipated energy can be replenished with strategically placed AC clock biases, as is done in various other superconducting digital technologies. Simulations promise good operating margins at speeds up to 4GHz with very low power dissipation. We name our logic family Conservative Reciprocal Asynchronous Ballistic Solitons (CRABS).

Quantum computers (QCs) offer significant advantages over traditional computers, including parallel computation and the ability to solve complex problems efficiently [1]. These advantages have driven research into various applications, such as artificial intelligence, cryptography, and security [2]. One critical challenge in QC development is integrating qubit
control circuitry into low-temperature or near-qubit-temperature environments to minimize
thermal noise and improve system performance. In this study, we propose a superconducting microwave generator with tunable amplitude, for qubit control. Our approach builds on the principles of pulse-generated microwaves, replacing part of the filter with a superconducting quantum interference device (SQUID). This
modification enables precise amplitude modulation of the output microwave signal by
adjusting the magnetic flux within the SQUID. Experimental results at 4.2K demonstrate the
successful operation of the microwave generator, confirming its feasibility for lowtemperature quantum applications. Moving forward, we aim to implement and evaluate this
system within a dilution refrigerator to further validate its performance in a quantum
computing environment.

We report the development of extremely low-power single-flux-quantum (SFQ) circuits toward digital signal processing near superconductor quantum bits. We fabricated the SFQ circuits using a lowered critical current density process (250 A/cm2) and low-voltage design (0.1 – 0.5 mV). We reduced the power consumption to 1/50 or 1/250 of the conventional SFQ circuits operating at 4.2 K. So far, we have designed several basic SFQ cells, including wiring elements, flip-flops, and logic gates with the four Nb planarized layer process and obtained the correct operation at low-frequency measurement at 0.3 K. In this work, we tested several SFQ circuits aiming to evaluate the operation at the mixing chamber stage of a dilution refrigerator. We successfully demonstrated the low-frequency operation of the standard cells and demultiplexer circuits with reasonable bias margins at 14 mK. We are currently working on the monolithic integration of the SFQ demultiplexer and multiple qubits as a simple example of cryogenic digital control of qubits.
This work was supported by JST Moonshot R&D Program Grant Number JPMJMS2067 and by VDEC of the University of Tokyo in collaboration with Cadence Design Systems, Inc. The test chips were fabricated at AIST Qufab.

The successful completion of the IARPA SuperTools project, which significantly advanced the state-of-the-art in superconductor electronic (SCE) design automation (EDA) tools, enabled SCE designers to synthesize and verify complex circuits such as 64-bit RISC processors. Advances under SuperTools included technology computer-aided design (TCAD), logic and clock synthesis, place-and-route and compact model extraction directly from layouts. A recent DARPA project on homomorphic encryption with SCE circuits demanded improvements in high-level synthesis, place-and-route and timing extraction tools. New lumped-element transmission line models were introduced to simulation tools to handle not just reflections, but also cross-coupling, dispersion and loss on inter-gate transmission lines in very large digital systems. Despite the maturity of large-scale digital circuit design and analysis tools, recent developments in the field have exposed a need to add EDA capabilities for superconductor quantum computing (SQC) design, analysis and verification. SQC end-user demand for tools that model and process flux trapping, vortex displacement, noise, high-precision extraction of weak magnetic coupling, and microwave frequency analysis for resonance and impedance has driven new directions in tool development. In this presentation, we discuss EDA advances post-SuperTools, including the new research and development efforts demanded by SQC applications.

Abstract—Recently, superconducting digital circuits have emerged as a promising technology in the post-Moore’s law paradigm. Utilizing Josephson junctions as the active switching element, superconducting digital circuits rely on the quantization of magnetic flux (fluxons) to encode binary information. Reciprocal Quantum Logic (RQL) is a leading superconducting logic family that has demonstrated fast, ultralow power operation with wide operating margins. Furthermore, it has shown promising scaling properties producing some of largest, most complex superconducting digital circuits to date.
While previous demonstrations of scaling have relied on custom design and physical layout of circuits, further scaling of superconducting digital circuits have been hindered by the lack of electronic design automation (EDA) tools. EDA tools have been essential to the realization and maturation of very-large scale integration (VLSI) of CMOS circuits. However, superconducting digital circuits introduce novel challenges which make off-the-shelf use of standard EDA tools incompatible for superconducting designs.
This paper introduces digital design using RQL and explores some of the difficulties encountered during synthesis, timing, and place & routing of RQL circuits. It also describes how these issues have led to novel solutions and features within the Cadence suite of EDA tools to realize digital superconducting circuits. With these advances in EDA tools, RQL technology is poised to achieve

Scaling up superconducting integrated circuits (SIC) represents a pivotal challenge in the field. Addressing this challenge necessitates a concerted effort across fabrication, design, and measurement teams. The development of Electronic Design Automation (EDA) tools is integral to this collaborative endeavor. These tools are essential for integrating new models and findings into the chip development process. Furthermore, EDA tools are invaluable for analyzing experimental data, thereby enhancing our understanding of circuit behaviors and facilitating more informed design improvements. Here, we present the JSIC-EDA system, a specialized suite of EDA tools developed for single flux quantum (SFQ) SIC designed to facilitate the scaling of on-site circuit development. The JSIC-EDA system integrates a 3D superconductor process model and a process design kit (PDK) database with state-of-the-art device timing, logic, and physical models, supporting comprehensive automated design processes for design and analysis on processes such as SIMIT-Nb03, SIMIT-Nb03P, SIMIT-Nb04, and other developing 3D processes. Ongoing development efforts are focused on creating new EDA algorithmic tools based on the JSIC-EDA system, aiming to further advance the design, analysis, and testing automation of superconducting integrated circuits as well as pioneering neuromorphic computing technologies.

The recent development of gate-voltage-controlled Josephson junctions (JJs) enables dynamic tuning of critical currents, unlocking new possibilities for superconducting circuit applications. We propose an extension to JoSIM, the open-source superconducting SPICE simulator, to incorporate models for gate-tunable Josephson junctions (GTJJs) based on recent experimental findings. By integrating voltage-dependent critical current dynamics, our model will enable circuit-level simulations of hybrid superconductor–semiconductor devices and nanobridge-based JJs. Inspired by recent advancements in gate-controlled superconductor–semiconductor hybrid junctions and gate-tunable nanobridge Josephson junctions, this work provides an essential tool for designing and optimizing tunable superconducting circuits, including voltage-controlled SQUIDs, cryogenic logic elements, and qubit control in superconducting quantum processors. The ability to modulate superconducting currents via gate voltage offers a new avenue for high-speed, low-power quantum computing architectures. Our approach ensures computational efficiency while maintaining accuracy, making JoSIM a valuable resource for advancing scalable, energy-efficient superconducting electronics. This contribution aligns with the growing need for software tools to model emerging superconducting and quantum computing technologies, bridging the gap between experimental breakthroughs and practical circuit design.

The balanced comparator, a pair of Josephson junctions, is a key building block and decision-making element for the Rapid Single Flux Quantum (RSFQ) logic family. The properties of the balanced comparator (BC) define the maximum clock frequency and bit error rate (BER) of RSFQ circuits. Comparators are well characterized by two parameters, the gray zone (GZ) and the gray zone threshold (GZT). Both parameters depend on the dynamic properties of a pair of junctions forming the BC and its surrounding circuitry. In addition, the gray zone depends on the thermal noise in Josephson junctions. The GZ and GZT parameters can be easily measured for various balanced comparators and be used for model-to-hardware correlations. It makes the balanced comparator a unique object to validate and calibrate any Josephson simulator by comparing measured and simulated characteristics, including both dynamic and noise properties. In this paper we used a set of balanced comparators designed for the SFQ5ee fabrication process at MIT Lincoln Laboratory to validate and calibrate the Synopsys PrimeSim HSPICE simulator. We were able to match experimental and simulated results and reproduce in simulations the main features observed experimentally and predicted theoretically. The list of the recommended design variations to validate a Josephson simulator is provided in the paper.

We present recent progress on the modelling of trapped vortices in superconducting niobium thin films using InductEx. By computing the Gibbs free energy for single-vortex states in microstrip and ground-plane structures, we quantify how temperature, geometry, and applied current impact vortex entry, separation, and motion. Our results show that as the temperature decreases below the critical temperature (Tc), the energy barriers grow significantly, making vortex motion increasingly difficult. Moreover, when a vortex resides in both the microstrip and ground plane, an additional energy barrier emerges from attempts to separate the vortices in the two layers. For the experimentally more common scenario of a vortex trapped solely in the ground plane, we determine the minimum current needed in an overlying microstrip to dislodge the vortex and drive it across the microstrip. This current requirement grows rapidly at lower temperatures, highlighting the challenges of flux management in superconducting circuits operating far below Tc. Finally, variations in microstrip width, isolation-layer thickness, and the presence of moats reveal the impact on energy barriers and vortex dynamics. These insights provide guidance for designing effective vortex control strategies to control vortex behaviour in superconducting circuits, enabling higher integration densities and enhanced operational stability.

Single Flux Quantum (SFQ) digital logic enables power-efficient high performance computing for quantum computing, neural networks, and space applications. However, scalability is hindered by high area overhead from gate-level path balancing and large splitter trees requiring excessive pipelining. Prior attempts to reduce area using multi-phase clocking and asynchronous designs have led to substantial throughput reductions, undermining SFQ’s performance advantages. To address this, we propose a timing-aware circuit optimization method that reduces area without sacrificing performance. Our approach accounts for gate delays while jointly optimizing splitter tree topology and gate-level clocking assignments to efficiently pipeline datapaths, achieving high performance with reduced area. Applied to multi-phase clocking, it relaxes strict path balancing constraints while maintaining full path balancing performance. Experimental results on benchmark circuits show a 34% area reduction at 50 GHz compared to prior FPB methods, while timing-aware multi-phase clocking achieves a 27% area reduction and a 30% latency reduction compared to 33 GHz FPB. These results highlight the potential for integrating timing-aware synthesis with physical design methodologies to further optimize SFQ circuits. Future work aims to incorporate wire delays and predictive placement for improved scalability and performance.

Keynote: Attractiveness of New Superconductor Electronics
Opened by π-Junctions

The DISCoVER (Design & Integration of Superconductive Computation for Ventures beyond Exascale Realization) Expedition mission is to explore novel superconductor electronics as a viable post-CMOS computing technology. The goal is to build a fully operational SuperSoCC, a system composed of superconductor electronic compute cores and memory, running together to execute applications at scale. Now entering its fourth year, the DISCoVER team includes seven universities and is centered at the University of Southern California (USC). The dispersed team must effectively combine new technologies, circuits, architectures, interfaces, and design methodologies into an important demonstration vehicle. This status report will focus on the systems engineering approach to a project that involves high level design down to fabrication process development. Key tradeoffs include the amount and temperature of the CMOS main memory and the interconnects to processors at 4 K.

Acknowledgement: DISCoVER is supported by a National Science Foundation (NSF) CISE Expedition in Computing award.
https://discoverexpedition.usc.edu/

Energy-efficient Rapid Single-Flux-Quantum (ERSFQ) circuits, combining low power consumption with high-frequency operation, present a promising solution for next-generation energy-efficient neuromorphic systems and high-performance computing. These circuits feature three distinct operational states: ERSFQ (with zero static power consumption), MIDSFQ, and RESFQ, with combined bias margins comparable to conventional RSFQ circuits. However, the practical implementation of ERSFQ technology has been constrained by the narrow bias margin of the ERSFQ state. To overcome this limitation, we present two novel optimization strategies: (1) a comprehensive analysis of the current compensation mechanism in feeding Josephson transmission lines (FJTLs), coupled with the development of a pulse-feeding technique that extends the lower margin boundary during measurement; and (2) an optimization protocol involving bias inductance adjustment and FJTL bias junction elimination to expand the upper margin boundary. Through the implementation of these methods on an 8-bit ERSFQ shift register, we achieved a substantial expansion of the ERSFQ state bias range from [94%, 100%] to [56%, 118%], representing a 930% improvement in bias margin. This research effectively addresses the challenge of limited bias margin in ERSFQ circuits, providing a more robust ERSFQ technology for future applications in neural networks and high-performance computing.

We have evaluated the propagation speed of impulses used for cell selection in the impulse-driven matrix memory. The memory has a special feature of high-speed operation exceeding tens of GHz. The feature originates from a single π-junction-SQUID used as a storage cell. The single π-junction-SQUID has two stable states with clockwise or counterclockwise circulating currents under no bias currents. The two states correspond to the binary signal stored in the memory cell.
In the actual design, we use a π-junction with sufficiently large critical current coupled with a conventional 0-junction, which acts as a single π-junction with a well-defined critical current. The barrier height is controlled by an impulse propagating on a word- and a bit-line to change the state. The maximum repetition frequency of the memory is determined by the time required to transmit those word and bit lines.
We fabricated the ring oscillator which contained a transmitter of an impulse, a receiver, and a 1250-micron-long PTL coupled with 8 memory cells through the bit-write line. The π-junctions were made with a Nb/Pd89Ni11/Nb structure on an Nb-based integrated circuit prepared with the AIST QuFab HSTP2 process. By fitting the numerical results, the speed of impulses is obtained to be 124 micron/ps. From this speed, we estimate the maximum repetition frequency of the 1kb-impulse-driven memory to be 78 GHz if we can use 1-micron process.

Superconductive single-flux-quantum (SFQ) circuits are well-suited for integrated circuits in stochastic computing, where signals are represented by the probability of a “1” appearing in a finite-length binary sequence. This suitability arises from their high-speed operation and the inherent ease of the stochastic behavior.
In stochastic computation, the correlation between binary number sequences (stochastic numbers, SNs) representing signals degrades computational accuracy. Large-scale arithmetic circuits require large fan-out signal splitters. However, due to the correlation problem, an SN cannot simply be split using a single-flux quantum (SFQ) splitter.
In this study, we propose a novel SN splitter that leverages frequency synchronization between parallelized superconductive random number generators (SRNGs). In an n-output SN splitter, the probability of a “1” appearing in the input SN is replicated across n SRNGs via frequency synchronization in the SFQ circuit. These SRNGs generate random number sequences that maintain the same probability of “1” occurrence as the input SN. Since the parallelized SRNGs produce mutually uncorrelated random outputs, the proposed SN splitter effectively mitigates the accuracy degradation caused by correlation between SNs.
We designed, implemented, and tested a 4-output SN splitter using a 10 kA/cm^2 Nb process. The high-speed operation of the SN splitter was successfully demonstrated at frequencies up to 30.3 GHz. In the presentation, we

Technology roadmaps for superconductor electronics (SCE) and quantum computing are under development within the framework of the International Roadmap for Devices and Systems (IRDS). Advanced fabrication processes are needed to allow SCE to achieve its potential. The most complex digital superconductor electronic circuit made to date has only a little over one million Josephson junctions, the switching elements at the heart of most SCE logic. Much larger circuit complexities are required to meet the demands of applications such as quantum computing support, machine learning, or large-scale digital computing. Key fabrication needs include materials with processing temperatures compatible with CMOS back end of line (BEOL), superconductor materials with higher critical temperatures, capacitors, smaller dimensions, more wiring layers, and junctions that are scalable to smaller dimensions or have different behaviors. Work towards development of a suitable fabrication stackup is presented with a focus on areas of greatest need.

Superconducting integrated circuits offer a promising solution to the challenges faced by modern information infrastructure primarily based on CMOS technology. In particular, adiabatic quantum-flux-parametron (AQFP) circuits have garnered attention due to their superior energy efficiency compared to conventional integrated circuits. However, one of the challenges in AQFP is the limited interconnect length between adjacent logic gates (< 0.7 mm) due to the cumulative inductance that attenuates the data signal amplitude. Keeping interconnects short is necessary to maintain a low bit-error-rate during data signal propagation. To compensate for this limitation, additional buffer/booster gates used as repeaters are required to recover data signals. This approach introduces additional latency due to the fully synchronized nature of AQFP. To address this, we propose a low-latency pathway implemented using rapid single-flux-quantum (RSFQ) technology, along with interface circuits between AQFP and RSFQ logic, as an alternative to the conventional AQFP buffer/booster repeaters. In this presentation, we will report on the experimental demonstration of a 1-bit AQFP-RSFQ microprocessor datapath in which the feedback is implemented using RSFQ logic and corresponding interface circuits. The latency of the feedback path is reduced by 67% at 5GHz speed. Our results confirm that computed data can be successfully written back to the AQFP registers through the RSFQ datapath at 100kHz test.

As energy efficiency is a critical constraint in data center computing and AI workloads dominate demand, superconducting digital logic technologies such as Adiabatic Quantum Flux Parametron (AQFP) devices offer a promising alternative. While individual devices show impressive characteristics, system-level benefits require full-stack evaluation. We introduce SuperLoop, an extension of the Timeloop+Accelergy accelerator modeling framework [1,2], to enable architectural design exploration of superconducting deep learning accelerators. Timeloop+Accelergy accepts configuration files describing workloads and hardware, then optimizes workload mapping and generates system-level energy, area, and throughput projections. SuperLoop extends this environment to support multiple superconducting logic families and memories, enabling modular tradeoff analysis and rigorous comparison with CMOS. We demonstrate SuperLoop by optimizing an AQFP-based accelerator inspired by the Eyeriss architecture [3]. Our results show a 60× energy reduction versus a 7nm CMOS equivalent, while accounting for a 10³ W/W cryogenic cooling overhead. SuperLoop supports a wide range of superconducting technologies, and we aim to expand its capabilities as we open-source the framework for the broader research community.
[1] A. Parashar et al., ISPASS 2019. doi:10.1109/ISPASS.2019.00042
[2] Y. Wu et al., ICCAD 2019. doi:10.1109/ICCAD45719.2019.8942149
[3] Y.H. Chen et al., IEEE JSSC (2017). doi:10.1109/JSSC.2016.2616357

We present the design, simulations, and testing of a Josephson sampler circuit with electrical bandwidth exceeding 100 GHz and potential applications for digital SFQ circuits. We simulated sampler circuit designs consisting of a single, hysteretic (latching) Josephson junction (JJ) as the logical sampling element (comparator) and a Faris pulser circuit that provides a fast (< 2 ps) sampling “strobe” pulse; we explored the impacts on sampler performance due to the signal-comparator coupling scheme used (galvanic, inductive, or capacitive), with the goal of balancing the highest sampler bandwidth with the minimum amount of distortion in the sampled waveform. Using these simulation results, we designed and characterized a JJ sampler chip operating at 3.6 K and fabricated using niobium JJs with amorphous Si barriers (Nb/a-Si/Nb) and critical current density Jc = 0.22 mA/μm2. Our cryocooled, fully-digital, and automated sampling system has an acquisition time of ∼ 1 s per data point and uses a binary search algorithm for comparator threshold determination; the binary search is also implemented in simulations to allow direct comparison between the measured and simulated sampled waveforms. With this sampler, we measured a 10% to 90% rise time of 3.3 ps for SQUID-generated step signals and a full width at half maximum of 2.5 ps for impulses from a Faris pulser circuit; both circuits were located on-chip and galvanically connected to the input of the sampler comparator.

We present the design and experimental characterization of a kinetic-inductance traveling-wave parametric amplifier (KI-TWPA) for sub-GHz frequencies. KI-TWPAs amplify signals through mixing processes supported by the nonlinear kinetic inductance of a superconducting transmission line. The device described here utilizes a compactly meandered TiN microstrip transmission line to achieve the length needed to amplify sub-GHz signals. It is operated in a frequency translating mode where the amplified signal tone is terminated at the output
of the amplifier, and the idler tone at approximately 2.5 GHz is brought out of the cryostat. By varying the pump frequency, a gain of up to 22 dB was achieved in a tunable range from about 450 to 850 MHz. TiN, as the nonlinear element, reduces the required pump power by roughly an order of magnitude relative to NbTiN, which has been used for previous KI-TWPA implementations. We also discuss preliminary results on the readout of FIR MKIDs in frequency translating mode using this KI-TWPA. This amplifier has the potential to enable high-sensitivity and high-speed measurements in a wide range of applications, such as quantum computing, astrophysics, and dark matter detection.

A Josephson comparator (JC), consisting of a pair of Josephson junctions, is a fundamental element in superconducting circuits and plays a key role in superconducting logic gates. It is also widely used in applications such as A/D conversion, high-speed random number generation, and probabilistic computation. In general, JCs exhibit a trade-off between operating speed and gray zone width. Notably, when the output probability is 0.5, the decision time increases, degrading the operating frequency of systems such as stochastic arithmetic circuits and Bayesian networks.
To prevent simultaneous switching (double-switching) in conventional JCs, the bias current must be reduced, or the preceding circuit’s drive capability must be weakened. We propose a novel JC operation that intentionally utilizes double-switching to produce a ‘1’ output, allowing operation with higher drive power and increased bias current. The issue of backward signal flow is mitigated by adding an escape junction.
We optimized JC parameters to ensure double-switching occurs with a 100% probability for a ‘1’ output. Simulations incorporating thermal noise show that the proposed operation reduces decision time by about 50% and narrows its distribution. The operating speed of a Bayesian network using JCs can be increased from 33 GHz to 54 GHz, assuming a 10 kA/cm² Nb superconducting fabrication process.

Accurately characterizing the near-field electromagnetic distribution of millimeter-wave/terahertz (mmW/THz) devices under operational conditions is critical for advancing ultrafast communication and quantum technologies. However, existing passive terahertz near-field microscopy techniques face persistent challenges in achieving both high spatial resolution and broadband detection. Here, we propose a novel passive terahertz near-field microscope leveraging a nanoscale tip-integrated Josephson junction. By exploiting the AC Josephson effect in the probe, our system enables coherent detection across an ultra-wide bandwidth (1–300 GHz) with sub-picowatt-level power sensitivity. This approach simultaneously resolves near-field amplitude, frequency, and phase information while providing sub-wavelength spatial resolution. We demonstrate its efficacy by analyzing electromagnetic standing wave modes in superconducting microwave quantum circuits and mapping electromagnetic compatibility (EMC) characteristics in mmW oscillator chips. The proposed technique offers a breakthrough methodology for iterative design optimization of mmW/THz integrated circuits and performance diagnostics of superconducting quantum systems, bridging a critical gap in high-fidelity near-field characterization for emerging quantum and terahertz technologies.

The “Josephson Arbitrary Waveform Synthesizer” (JAWS) was developed at PTB for many years. Based on a sophisticated multi-layer thin film technology, more than 40 000 SNS Josephson junctions can be integrated into one JAWS chip. Arbitrary waveforms with an amplitude of more than 1 V RMS in a frequency range up to ca. 1 MHz were synthesized.
To realize higher output voltages and to reduce the complexity/costs of the JAWS setup, it is necessary to increase the output voltage per JAWS chip and decrease the JAWS pulse drive lines.
One approach is the use of an optical pulse-drive. For this, a cryo-package of several high-speed photodiodes is realized by flip-chip technology. These photodiodes are operated at 4 K in the close vicinity of the JAWS arrays. So far, a four-channel optical drive with 6000 junctions in total was established, providing an output voltage of approx. 100 mV PP.
Another approach was realized by implementing on-chip Wilkinson power dividers. Here, an output voltage of 0.6 V RMS with 36 000 junctions was achieved. To further improve these power-dividers new compact lumped element dividers have been developed. First results will be presented.
To extend the JAWS to higher signal frequencies, the so-called RF-JAWS is developed at PTB, too. Frequencies of up to 10 GHz were realized. The latest RF-JAWS circuit design generations will be introduced, including on-chip diplexer filter structures to improve the performance and quantum precision of the JAWS output.

Josephson arbitrary waveform synthesizers (JAWS), which are driven with pulses, are used to realize the SI unit of volt for ac waveforms [1]. They and their Josephson pulse generator (JPG) counterparts can also be used to drive qubits [2]. Functional quantum computers need thousands of control lines, which conduct heat. To minimize the thermal leakage, one could use optical signal lines, where heat conduction is minimal and multiple signals can be packed into single line [3]. The optical signals can also be used to drive JAWS [4]. However, driving qubits with optically controlled JAWS is yet to be demonstrated. Multiple processes exist for JAWS fabrication including e.g. growing superconductor – normal metal – superconductor (SNS) trilayers [5]. Here we report on optically driven JAWS fabricated with sidewall passivated spacer (SWAPS) [6] technology. SWAPS is a scalable wafer level process that has been successfully used to fabricate e.g. Josephson parametric amplifiers (JPA) [7] and superconducting quantum interference devices (SQUIDs) [8].
[1] Appl. Phys. Lett. 68, 3171 (1996).
[2] Appl. Phys. Lett. 122, 192602 (2023).
[3] Nature 591, 575 (2021).
[4] Appl. Phys. Lett. 119, 032601 (2021).
[5] IEEE Transactions on Appl. Supercond. 19, 981 (2009)
[6] Supercond. Sci. Technol. 30, 125016 (2017)
[7] Supercond. Sci. Technol. 31, 105001 (2018)
[8] IEEE Transactions on Appl. Supercond. 28, 1600204 (2018)

Keynote: Superconducting photon detectors

Quantum photonics relies on interfacing different technologies under mutually compatible operating conditions. While integrated optics is typically optimised for room temperature operation, superconducting nanowire single photon detectors (SNSPDs) require cryogenic operating conditions. Recently, we have demonstrated integrated photonic modulators driven by the electrical output of SNSPDs, demonstrating low-power cryogenic opto-electronic signal processing and detector read out [1]. We use titanium in-diffused waveguides in lithium niobate as our nonlinear and electro-optic integration platform, which is very useful for cryogenic prototyping and informs the design of more scalable nonlinear and electro-optic integration platforms, in particular lithium niobate on insulator (LNOI).
In this talk I will discuss our latest results implementing a cryogenic feed-forward opto-electronic circuit, which can selectively manipulate a quantum state based on a desired measurement outcome [2]. The single photon detection with an SNSPD, amplification with CMOS ICs and electro-optic modulation in lithium niobate waveguides is performed entirely within a cryostat at 0.8K. The tight integration allows us to minimize the latency between the measurement result at the single photon level and the modulation.
[1] Thiele et al., Optics Express, 31(20), 32717-32726 (2023)
[2] Thiele et al., arXiv preprint arXiv:2410.08908. (2024)

Superconducting nanowire single-photon detectors (SNSPDs) can potentially offer a route to true photon-counting detector arrays in the mid and far-infrared. This would result in an entirely new scientific camera, one that would find uses in a rich variety of fields, from biological imaging and remote sensing to large astronomy projects and dark matter detection.

Mid-infrared SNSPD array development requires three key advancements: single-photon sensitivity at long wavelengths, efficient coupling of infrared-photons to the detector and scalable multiplexed readout techniques to scale to large arrays. In this talk I will outline the progress made to date on each area, then discuss a variety of remaining challenges and our efforts to solve them.

Superconducting nanowire single-photon detectors (SNSPDs) became the golden standard in single-photon counting, enabling key photonic quantum applications. Recent advances further expanded their capabilities, demonstrating that, beyond their exceptional performance in single-photon detection, SNSPDs also posses intrinsic photon-number resolution (PNR) up to a few photon numbers [1]. Mastering this would allow high-fidelity quantum light detection without requiring expensive detector arrays or complex multiplexing schemes.

Intrinsic PNR in SNSPDs is governed by the dynamics of resistive domains, which manifest in the timing of voltage response pulse following photon absorption. When multiple photons are absorbed, they may generate non-overlapping resitive domains, with their combined dynamics encoding photon number information. High-frequency readout electronics can decode this information from the voltage pulse. However, domain overlap, as well as timing jitter caused by fluctuations [2], distort photon number discrimination. Here, we present an intrinsic PNR model validated against experimental results from a commercial SNSPD. We discuss the fundamental constraints on the resolvable optical pulse duration and photon number imposed by overlapping effects and thermal fluctuations[2]. Our findings provide a framework for optimizing SNSPDs for photon-number-resolving applications.

[1] JW Los et al., APL Photonics 9, 066101 (2024)
[2] AD Semenov et al., Phys. Rev. B 102 (2024)

High-fidelity photon number resolution (PNR) single-photon detectors are a key technology, but remain challenging in numerous quantum information and quantum metrology applications. Superconducting transition edge sensor has good PNR performance, but it has some problems such as slow detection speed, timing jitter, cooling and complicated readout. Here, we report an important step forward in the research of a high-fidelity PNR single-photon detector that combines near-limit efficiency detection and large-scale spatial reuse techniques using segmented double-layer superconducting nanowires. Thanks to the synergistic effect of the double-layer nanowires, the unique double-layer structure at the top of the dielectric mirror ensures near-limit detection efficiency and high signal-to-noise ratio readout. The segmented structure of each segment is shunt by the resistor to form a spatial multiplexing scheme, which constructs the mapping relationship between the pulse amplitude and the incident photon. We have prepared 8-pixel devices with 98% system detection efficiency (SDE). Further detector tomography revealed that the 2-photon and 3-photon fidelity of the 8-pixel device was 75% and 52%. In addition, our 8-pixel series nanowire detector prepared based on the 2-SNAP structure maintained a high count rate of 100 MHz at -3dB-SDE. Due to its near-limit efficiency, high photon number resolution, fast detection speed and high temporal resolution, we believe that the detector will attra

Superconducting nanowire single-photon detectors (SNSPDs) are crucial for quantum optics, quantum communication, and deep-space laser communications, offering high detection efficiency, low dark counts, and excellent timing performance. However, improving efficiency in the near- to mid-infrared, remains challenging. Ion irradiation has recently emerged as a promising post-processing method for optimizing SNSPD performance.
This work investigates the effects of helium ion irradiation on the thermal properties of NbN-based SNSPDs. We examine the evolution of thermal boundary conductance (TBC) under varying ion fluences (0–1.1×10⁷ ions/cm²), observing a nearly linear decrease with increasing fluence, followed by saturation around 9×10⁶ ions/cm². Measurements of inelastic scattering rates and hotspot relaxation times show a significant increase after irradiation. Furthermore, transmission electron microscopy (TEM) reveals irradiation-induced vacancy defects at the NbN/SiO₂ interface, leading to prolonged thermal relaxation times. Together with modifications in electrical properties, these changes contribute to enhanced internal detection efficiency in irradiated devices.
Our findings provide new insights into post-processing of SNSPDs via ion irradiation, offering a pathway to improve detection efficiency and tune thermal properties in superconducting devices. This work also advances the understanding of defect engineering in superconducting thin films and their device.

Ultra-fast single-photon detectors with high current density and operating temperature can benefit space and ground applications, including quantum optical communication systems, lightweight cryogenics for space crafts, and medical use. Despite decades of dedicated research, progress in superconducting devices utilizing high critical temperature (Tc) materials has remained relatively modest. This is due to several factors, including the challenges associated with high-Tc material synthesis and device fabrication, the complexity of their underlying physics, and the thermal management difficulties inherent in higher-temperature operation. However, recent advancements in MgB₂ thin-film growing [1] and defect engineering [2] have opened new possibilities for developing MgB₂-based detectors and electronics, paving the way for enhanced performance and broader applications.
In my talk, I will overview the current state of MgB₂-based detectors and electronics, highlighting key challenges and emerging applications in high-energy physics and neuromorphic science. I will also present our recent studies on thin films and nanostructures, revealing new observations that offer valuable insights into the underlying mechanisms of MgB₂-based devices.

[1] S. Cherednichenko and et al, Superconductor Science and Technology 34.4 (2021): 044001.
[2] Ilya Charaev and et al, Nature Communications 15.1 (2024): 3973.

Superconducting Quantum Interference Devices (SQUID) are excellent sensors for high-performance electromagnetic (EM) geophysical prospecting. The SQUID chips exhibit low magnetic field noise level of 3 fT/√Hz, and the swing of the SQUID V-Φ curve reaches ~150 μV. This characteristic enables broadband signal acquisition up to 3 MHz with a flat spectral response for the sensor.
The experimental configuration employed the short offset TEM (SOTEM) with the survey line 500-2000 m away from the electrical transmitting line. Quantitative comparative analysis of SQUID performance against conventional induction coil receivers (Phoenix V8 system) was conducted. Post-normalization data revealed the SQUID system achieved a noise floor of 0.02 nT/s, which was improved by two orders of magnitude compared to 3 nT/s for the coil receiver.
The geophysical explorations were carried out at more than 20 metallic deposits. A notable achievement was the successful identification of the gold-bearing structure concealed beneath approximately 200 m thick low-resistivity overburden. In the porphyry copper deposit exploration across ten parallel survey lines, the exploration result fitted the drilling data well until 2000 m depth. The maximal exploration depth of 3400 m was achieved at a deep-buried lithium brings according to the resistivity profiling map.
HTc SQUID is also fabracated by helium-ion-beam process with noise level of 100fT/√Hz. It will be a more convenient method for TEM prospecting.

The dc SQUID is an established application of superconductor technology. The key feature is its sensitivity to physical quantities that can be transduced into magnetic flux threading the SQUID loop. This translates into numerous applications, e.g., low-temperature thermometry or current sensing for electrical metrology. We present superconducting “fine-pitch” signal input coils with sub-micrometer line width and pitch - down to 150 nm, more than an order of magnitude smaller than current state-of-the-art coils - to be integrated into existing Nb/Al-AlOx/Nb-based sensor designs. The aim is to reduce inductive losses of the signal-to-SQUID coupling, without compromising the overall device layout. In a SQUID current sensor, it is crucial to maximize the inductive coupling constant k between the signal input coil and the SQUID loop to achieve a low coupled energy sensitivity εc = (1/k²)xε, where ε is the intrinsic energy sensitivity. Fine-pitch input coils will both increase k and extend the range of input coil inductances for our existing sensor types, up to tens of µH. Under optimum conditions, ε ∝ √LC with L - SQUID loop inductance and C - capacitance associated with the Josephson junctions (JJ). Reducing the JJ area will lower both C and εc. To this end, we are also refining our process to fabricate JJs with sub-micrometer lateral size. This contribution will provide details on the fabrication process and design aspect of the sensors, as well as characterization results.

Quantum sensing provides advanced technologies which significantly improve sensitivity and accuracy for sensing changes of motion, gravity, electric and magnetic field. Therein, sensors for magnetic field detection, so-called quantum magnetometers, are one of the most promising technological realizations useful for mineral exploration.
In this work, we present our advanced 3D vector magnetometer based on LTS Superconducting QUantum Interference Devices (SQUIDs) which enables to measure the full vector of the Earth’s magnetic field in mobile operation for passive electromagnetic exploration. The SQUIDs are multi-loop structures using sub-µm sized niobium Josephson junctions and have thus large voltage swings of >130µV and a low intrinsic white noise floor of about 2 fT(rms)/sqrt(Hz). Three orthogonally oriented magnetometers are read out by a flux counting electronics which provides a large dynamic range of >32bit, a slew rate exceeding 1MPhi0/s or equivalently 0.54 mT/s, and a bandwidth ranging from DC to 32kHz.
We will provide insights about the instruments performance in exploration e.g. in Namibia. By data post-processing, transfer functions are calculated and later inverted for deriving electrical conductivity anomalies for exploration depths exceeding 1km.
Acknowledgement: We gratefully acknowledge the DESMEX team. This work was partly supported by the Eurostars program in QMAG (no. 01QE1710) and by BMBF in the DESMEX (no. 033R130) and DESMEX-Real project (no. 033R385).

SQUID Series Arrays (SSAs) are widely used amplification devices for cryogenic readout chains such as Transition Edge Sensor (TES) matrices for space observation (doi: 10.1007/s10686-022-09880-7) or quantum science (doi: 10.1063/5.0149478). Either wiring-related external or on-chip internal parasitics often cause SSAs to show instabilities, which may limit the obtainable gain from a SSA design or may constrain the cryogenic setup that can be made stable. We shall show a rough model of typical parasitics in a setup and estimate the associated stability criteria. Modelling is backed up with experimental data from SSAs fabricated at VTT ?(doi: 10.1109/TASC.2021.3060356) and operated at T = 4.2 K. In experiments the SSA has been augmented with a set of controlled external parasitic elements and the instability threshold observed.

Magnetoneurography (MNG) [1] is a new SQUID biomagnetic detection method to measure human nerve current flow [2], which has high clinical application value in the diagnosis of neurological diseases [3], [4]. Since the strength of the MNG signal is about several tens of fT, and the signal frequency band is in the hundreds of Hz [5] , it is mainly detected by SQUID, and it is difficult to effectively measure MNG by other detectors such as Optically Pumped Magnetometers (OPMs) until now. In recent years, a prototype has been developed in Japan and MNG detection based on patch electrode stimulation has been carried out[6]. At present, we have built a SQUID MNG system, which achieves the frequency-domain noise level of about 2.8 fT/sqrt(Hz) and the time-domain noise level of about 24 fT. Based on the system, we carried out SQUID MNG measurement and detected MNG signal with intensity of about 100 fT. MNG imaging was realized and the nerve conduction wave velocity of about 50 m/s was detected. In addition, we have also cooperated with the hospital to carry out research work on MNG detection combined with traditional Chinese medicine acupuncture methods, which will help in the diagnosis and treatment of nerve conduction diseases.

Keynote: Superconducting strip photon detectors and applications

Quantum technologies, especially quantum computing, will play a groundbreaking role in technology, economy, and social developments and are therefore considered to be a game changer in various branches. The core element for quantum computation are quantum bits (qubits), which can be realized by superconducting implementations. Nowadays a promising and commonly used qubit type is a transmon. It consists of one or two Josephson junctions which are shunted by a big capacitance. In most cases the qubits are integrated with coplanar waveguide resonators and transmission lines to provide a low loss read out. Recently, scaling up the number of qubits is the main task for realizing quantum computers and, thus, wafer-scale fabrication technologies for the qubits in combination with beyond 2D integration technologies are essential.
In our presentation, we provide latest results on our research on wafer-scale fabrication and characterization of the superconducting quantum circuits with a special emphasis on the transmon qubit environment and integration technologies. We discuss different approaches on fabricating coplanar waveguide resonators and evaluate their quality factors. Within the scope of scalability and increased packaging density, we present aluminum air bridges as a part of our integration technology. We discuss their fabrication process and demonstrate their superconducting properties as well as their implementation into the superconducting quantum circuits.

Growing the number of qubits inside a processor unit is a challenging task in development of quantum computer. 3D integration emerges as a crucial technology for the advancement and scalability of superconducting qubit-based processor, with through-silicon vias (TSVs) serving as a fundamental component in facilitating high-density interconnects. In this study, we introduce superconducting TSVs that eliminate the use of deposited amorphous dielectrics, which significantly reduces microwave loss and ensures seamless compatibility with high-fidelity qubits. Our innovative approach effectively addresses the critical challenges associated with the 3D integration of quantum processing units (QPUs), thereby enhancing both coherence and scalability.
We further advance TSV technology by substituting the traditionally fragile metallic membrane with a robust silicon-based layer. This modification not only improves mechanical stability but also increases chip yield, making it a more reliable option for manufacturing. The enhanced design strengthens the overall TSV structure and promotes the growth and patterning of additional functional layers, thereby extending the versatility of our integration platform. Our findings underscore that these superconducting TSVs offer a scalable solution for the next generation of quantum computing architectures, paving the way for more efficient and powerful quantum systems.

Acknowledgement: OpenSuperQPlus100 project

The single flux quantum (SFQ) circuit with Josephson Junction is a promising candidate for high-performance computing due to its high speed and low loss dissipation. In order to improve the integration of SFQ circuit chips, the three-dimensional multi-chip module (3D-MCM) technology would be an effectively way. Through silicon via (TSV) is an important interconnection technology for realizing 3D-MCM. However, superconducting integrated circuits have low-temperature operating conditions (4.2 K) and weak signals (mV), which bring the new requirement and challenges for the vertical interconnection of 3D-MCM, i.e. The TSV interconnect should preferably be superconductive so as to ensure the lowest-loss transmission of the chip-to-chip SFQ signals.
To achieve superconducting TSVs, we proposed a niobium-based vertical TSV method. We achieved vertical TSVs with low-roughness TSV sidewalls by DRIE process, and eliminated the scallop pattern defects by thermal oxidation process and BOE etching process; then we used double-side magnetron sputtering method to deposit niobium (Nb) thin films inside the TSVs, and completed the interconnections between Nb-TSVs by Nb redistribution layer (RDL) on the double side of the interposer wafer. The electrical tests showed that the superconducting transition temperature (Tc) of the fabricated Nb-TSV reaches 6.2 K and the critical current (Ic) of Nb-TSV exceeds 100 mA, which can meet the requirements of superconducting integrated circuits.

An unsolved problem for superconducting electronics is the lack of a scalable cryogenic memory technology. Superconducting memories have scaling limitations and semiconducting memories may not be compatible with the speed and energy-efficiency of superconducting logic. A cryogenic memory technology designed specifically for integration with superconducting devices is required.

Magnetic materials are promising for improved energy efficiencies in memories, but the fringe magnetic field can significantly affect the operation of superconducting electronic devices. In this talk we will explain how this problem might be overcome with the rare-earth or lanthanide nitrides, ferromagnetic semiconductors where the presence of spin and un-quenched orbital magnetic moments allows a much wider control over the magnetic properties than in other materials. Using solid solutions of lanthanide nitrides such as (Gdx,Sm1−x)N we demonstrate independent control of the net-magnetisation and coercive field.

We will present our work on two memory concepts based on the highly tunable magnetic
properties of the lanthanide nitrides. We will show their incorporation into trilayer switchable magnetic dot memory elements, readable by standard Josephson junctions. We will also show our work using the lanthanide nitrides as the barrier layer in magnetic Josephson junctions, towards fast, scalable and low power-dissipation memory devices ready to integrate with superconducting electronics.

To investigate the influence of temperature on high-temperature Josephson junctions, this study develops an empirical model that examines the phenomenon across various implementations. We analyze multiple Josephson junctions fabricated using different high-temperature superconducting materials, including YBa₂Cu₃O₇₋δ (YBCO) and Bi₂Sr₂CaCu₂O₈₊δ (BiSCCO), as well as distinct fabrication techniques such as bicrystal and step-edge Josephson junctions. By systematically modeling their behavior under varying thermal conditions, we aim to construct a predictive framework for understanding the temperature dependence of these junctions. The empirical model obtained will be compared with classical theoretical models to assess its accuracy and predictive capabilities. These insights will contribute to optimizing the performance of high-temperature superconducting detectors and advancing their applicability in terahertz sensing and quantum technologies.

The development of helium ion beam-fabricated Josephson junctions represents a transformative breakthrough for high-temperature superconducting (HTS) electronics. These junctions exhibit well-defined insulating barrier characteristics and improved performance compared to earlier HTS junction technologies. Beyond their application in circuit fabrication, these junctions enable in-plane tunneling spectroscopy, offering new insights into the anisotropic transport properties of YBa₂Cu₃O₇₋δ (YBCO). By leveraging this understanding, we can design circuits that are more resilient to the detrimental effects of anisotropy, improving the robustness and scalability of HTS devices.
These advances coincide with significant progress in HTS thin film growth. Reactive co-evaporation (RCE) now enables the deposition of large-area, high-quality YBCO thin films with improved uniformity and reduced defect densities, overcoming previous limitations in material scalability. Together, these breakthroughs provide a compelling case for revisiting HTS superconducting electronics, enabling new opportunities in nanoscale superconducting quantum interference devices (nanoSQUIDs) for ultra-sensitive detection and quantum flux parametron (QFP) logic for energy-efficient computing. The combination of precision junction fabrication and high-quality thin films sets the stage for a new generation of high-Tc superconducting circuits with applications in quantum sensing and cryogenic computing.

Stochastic Computing (SC) is a computational paradigm that encodes numerical values within the probability of logic ‘1’s in a stochastic bitstream. Utilizing SC enables neural network implementations to achieve improved scalability and ultra-low hardware footprint . This work proposes SuperSIM+, an extension of the benchmarking framework SuperSim designed for neural networks using superconducting Josephson devices. By expanding its functions beyond the existing single-bit and multi-bit Process-In-Memory (PIM) designs, SuperSIM+ enables comprehensive SC-based neural network (SCNN) benchmarking. Specifically, the proposed SuperSIM+ support superconducting SCNNs by incorporating stochastic memory, probabilistic multiplication, superconducting pulse merging-based accumulation, and efficient activation using adjustable flux storage loops. Several classical neural network models trained on the MNIST and CIFAR-10 datasets are employed to validate our framework in SC simulation, including computational accuracy, hardware cost, energy consumption, and overall latency .
Key words: Stochastic Computing, System Simulations, Neural Network
Acknowledgment:
This work was supported by JST FOREST Program (Grant Number JPMJFR226W, Japan) and JSPS KAKENHI Grant Number JP22H0220 and 23K28055.

This paper proposes a reconfigurable Single Flux Quantum (SFQ) accumulator architecture with multi-precision support, specifically optimized for energy-efficient neural inference in superconducting computing systems. By leveraging hierarchical Toggle Flip-Flop (TFF) cascading and asynchronous pulse-driven logic, the design dynamically adapts to varying operand bit-widths. The modular architecture employs a hybrid of TFF-based state propagation and clockless carry merging, enabling scalable accumulation for multi-operand sequences. With configurable output truncation and adaptive clock gating, the design supports continuous data streaming at up to 142.8 GHz.

Artificial Neural Networks (ANNs) are computational models inspired by the human brain and play a crucial role in processing large-scale data in artificial intelligence. To enhance energy efficiency and improve operational speed, ANN hardware implementations have been actively developed. This study focuses on the design of a single-flux quantum (SFQ) neuron circuit incorporating a Rectified Linear Unit (ReLU) activation function for superconducting ANN hardware.
The ReLU activation function is particularly well-suited for ANNs, as it mitigates the gradient loss problem in large-scale neural networks. The proposed circuit primarily consists of an SFQ resettable delay flip-flop (RDFF). When the input data frequency exceeds the reset input frequency, the RDFF outputs SFQ pulses at a frequency corresponding to the difference between the data and reset input frequencies. Conversely, when the input data frequency is lower than the reset input frequency, no output is generated. Therefore, the ReLU-shaped output frequency as a function of the input data frequency is obtained by using this circuit.
The circuit was fabricated using the 10 kA/cm² Nb High-Speed Standard Process at AIST and evaluated at 4.2 K. Experimental results confirmed the correct operation of the ReLU activation function up to an input frequency of 40 GHz.

A rotating superconductor exhibits various physical effects, however, the dynamics of rotating vortices remain relatively unexplored. A solid theoretical foundation is the necessary precursor for experimental validation and application. This work presents key mathematical findings, including an approximation for the number of single-fluxon pinning sites in the superconductor and the dependence of the quantum fluxon on the bulk rotation leading to the quantization of the London moment. These results were derived from the superfluid-analogous behavior of supercurrents and the Abrikosov magnetic field structure. Beyond fundamental theory, this study shows that the rotation dependence can then be applied to multi-input logic gates for vortex based computation. In particular, vortex motion patterns and pinning energies are found to vary with rotation and thus shown to mimic neural network behavior. Arrays of variable vortex pinning sites were simulated, and their rotation-sensitive responses were perturbed with small currents to train a machine learning algorithm in recognizing vortex configurations patterns, similar to how biological neurons adapt yet surpassing traditional computing systems. Unlike established vortex computation systems, the recognition and control of rotation as an input provides greater flexibility and thus increased possibilities for application from classical to quantum computing.

The intrinsic dynamics of Josephson Junctions naturally form a good candidate for modelling biological neurons. Following basic neuroscientific principles, we demonstrate that a network of Niobium-Neurons with a truncated synapse model can behave like a neural network of excitatory and inhibitory neurons in the human brain. We developed an extended Niobium Neuron Soma model that includes multiple outward connections using single-flux-quantum building blocks and scaling as well as sign switching of the created current spikes using a modified Josephson comparator. This neuron exhibits features typical for leaky integrate-and-fire neurons with equal-strength outward connections necessary to build all-to-all or sparsely connected networks, two crucial connectivity types to represent neural circuits in the human brain. The resulting network shows input rate dependent state switching between asynchronous and synchronous firing and is a first demonstration towards the study of large-scale brain dynamics with Josephson Junction based technology. This bears the potential of brain network simulations with computation speeds orders of magnitude faster than both semiconductor realizations and biological neural networks.