Superloop: Architecture Modeling for Superconducting AI Accelerators
As energy efficiency is a critical constraint in data center computing and AI workloads dominate demand, superconducting digital logic technologies such as Adiabatic Quantum Flux Parametron (AQFP) devices offer a promising alternative. While individual devices show impressive characteristics, system-level benefits require full-stack evaluation. We introduce SuperLoop, an extension of the Timeloop+Accelergy accelerator modeling framework [1,2], to enable architectural design exploration of superconducting deep learning accelerators. Timeloop+Accelergy accepts configuration files describing workloads and hardware, then optimizes workload mapping and generates system-level energy, area, and throughput projections. SuperLoop extends this environment to support multiple superconducting logic families and memories, enabling modular tradeoff analysis and rigorous comparison with CMOS. We demonstrate SuperLoop by optimizing an AQFP-based accelerator inspired by the Eyeriss architecture [3]. Our results show a 60× energy reduction versus a 7nm CMOS equivalent, while accounting for a 10³ W/W cryogenic cooling overhead. SuperLoop supports a wide range of superconducting technologies, and we aim to expand its capabilities as we open-source the framework for the broader research community.
[1] A. Parashar et al., ISPASS 2019. doi:10.1109/ISPASS.2019.00042
[2] Y. Wu et al., ICCAD 2019. doi:10.1109/ICCAD45719.2019.8942149
[3] Y.H. Chen et al., IEEE JSSC (2017). doi:10.1109/JSSC.2016.2616357