Superconductive single-flux-quantum (SFQ) circuits are well-suited for integrated circuits in stochastic computing, where signals are represented by the probability of a “1” appearing in a finite-length binary sequence. This suitability arises from their high-speed operation and the inherent ease of the stochastic behavior.
In stochastic computation, the correlation between binary number sequences (stochastic numbers, SNs) representing signals degrades computational accuracy. Large-scale arithmetic circuits require large fan-out signal splitters. However, due to the correlation problem, an SN cannot simply be split using a single-flux quantum (SFQ) splitter.
In this study, we propose a novel SN splitter that leverages frequency synchronization between parallelized superconductive random number generators (SRNGs). In an n-output SN splitter, the probability of a “1” appearing in the input SN is replicated across n SRNGs via frequency synchronization in the SFQ circuit. These SRNGs generate random number sequences that maintain the same probability of “1” occurrence as the input SN. Since the parallelized SRNGs produce mutually uncorrelated random outputs, the proposed SN splitter effectively mitigates the accuracy degradation caused by correlation between SNs.
We designed, implemented, and tested a 4-output SN splitter using a 10 kA/cm^2 Nb process. The high-speed operation of the SN splitter was successfully demonstrated at frequencies up to 30.3 GHz. In the presentation, we

A Josephson comparator (JC), consisting of a pair of Josephson junctions, is a fundamental element in superconducting circuits and plays a key role in superconducting logic gates. It is also widely used in applications such as A/D conversion, high-speed random number generation, and probabilistic computation. In general, JCs exhibit a trade-off between operating speed and gray zone width. Notably, when the output probability is 0.5, the decision time increases, degrading the operating frequency of systems such as stochastic arithmetic circuits and Bayesian networks.
To prevent simultaneous switching (double-switching) in conventional JCs, the bias current must be reduced, or the preceding circuit’s drive capability must be weakened. We propose a novel JC operation that intentionally utilizes double-switching to produce a ‘1’ output, allowing operation with higher drive power and increased bias current. The issue of backward signal flow is mitigated by adding an escape junction.
We optimized JC parameters to ensure double-switching occurs with a 100% probability for a ‘1’ output. Simulations incorporating thermal noise show that the proposed operation reduces decision time by about 50% and narrows its distribution. The operating speed of a Bayesian network using JCs can be increased from 33 GHz to 54 GHz, assuming a 10 kA/cm² Nb superconducting fabrication process.