Northrop Grumman has developed a process to fabricate Josephson digital integrated circuits based on the Reciprocal Quantum Logic (RQL) gates. The chips have 13 niobium layers: 10 wiring layers (with 0.25-µm feature size) plus 3 ground plane layers. To maintain high quality, the first 10 Nb layers are embedded in a silicon-rich nitride that is deposited at high temperature. After the Josephson junctions are formed, the last 3 layers of insulator are deposited at 150°C. Shift registers were fabricated to measure process yields with recent 2,700-bit shift registers, containing 43,200 junctions each, demonstrating better than 50% yield of working circuits. The best result had 1.5 million junctions working at 1 GHz in 93,872 total shift register bits on a 10-mm x 10-mm chip. Test capabilities include 4 Kelvin wafer probing and multiple closed cycle refrigerators that each hold 16 packaged chips that have measured thousands of chips per year. Process development has not only adapted methodologies from CMOS to superconducting electronics (SCE), but also created new techniques to observe superconducting-specific properties. By incrementally increasing performance, NGSC has and is continuing to mature a SCE process while matching it with both design and test capabilities that enable beyond-CMOS capabilities, taking SCE from the exhibition of hero devices to a higher standard of performance.