The DISCoVER (Design & Integration of Superconductive Computation for Ventures beyond Exascale Realization) Expedition mission is to explore novel superconductor electronics as a viable post-CMOS computing technology. The goal is to build a fully operational SuperSoCC, a system composed of superconductor electronic compute cores and memory, running together to execute applications at scale. Now entering its fourth year, the DISCoVER team includes seven universities and is centered at the University of Southern California (USC). The dispersed team must effectively combine new technologies, circuits, architectures, interfaces, and design methodologies into an important demonstration vehicle. This status report will focus on the systems engineering approach to a project that involves high level design down to fabrication process development. Key tradeoffs include the amount and temperature of the CMOS main memory and the interconnects to processors at 4 K.

Acknowledgement: DISCoVER is supported by a National Science Foundation (NSF) CISE Expedition in Computing award.
https://discoverexpedition.usc.edu/

Technology roadmaps for superconductor electronics (SCE) and quantum computing are under development within the framework of the International Roadmap for Devices and Systems (IRDS). Advanced fabrication processes are needed to allow SCE to achieve its potential. The most complex digital superconductor electronic circuit made to date has only a little over one million Josephson junctions, the switching elements at the heart of most SCE logic. Much larger circuit complexities are required to meet the demands of applications such as quantum computing support, machine learning, or large-scale digital computing. Key fabrication needs include materials with processing temperatures compatible with CMOS back end of line (BEOL), superconductor materials with higher critical temperatures, capacitors, smaller dimensions, more wiring layers, and junctions that are scalable to smaller dimensions or have different behaviors. Work towards development of a suitable fabrication stackup is presented with a focus on areas of greatest need.