Increasing the integration scale and operating speed of superconductor digital circuits requires increasing the critical current density, Jc of Josephson junctions (JJs) and reducing their area. In the current SFQ5ee process at MIT Lincoln Laboratory (MIT LL), externally shunted Nb/Al-AlOx/Nb JJs are used. The area occupied by the JJs can be reduced by 10x by implementing self-shunted junctions not requiring shunt resistors. For Nb/Al-AlOx/Nb JJs, the sufficient self-shunting occurs at Jc ~600 µA/µm2. Therefore, the next node of the superconductor electronics fabrication process at MIT LL targets JJs with Jc= 600 µA/µm^2 and the minimum JJs diameter of 0.35 µm, a 2x reduction in comparison to the SFQ5ee node. We will present data on the fabrication and properties of the self-shunted junctions, their on-chip and across-wafer uniformity, and wafer-to-wafer Jc repeatability. SNS-type JJs could be a potential alternative to high-Jc, tunnel-barrier-based JJs, where N is a highly disordered, high-resistivity “poor” metal or a heavily doped semiconductor. We have been developing JJs using nonsuperconducting NbNx (x>1) barriers and stoichiometric NbN, or Nb, electrodes. We present fabrication details and electrical properties of Nb/NbNx/Nb and NbN/NbNx/Nb junctions, in a range of barrier thicknesses from 5 nm to 20 nm, deposited by reactive sputtering and incorporated in a fully planarized multilayered process, and provide comparison to the properties of Nb/Al-AlOx/Nb junctions.