The adiabatic quantum-flux-parametron (AQFP) [1] is an ac-biased logic family known for its ultra-low switching energy of approximately 1.4 zJ per Josephson junction (JJ) at 5 GHz, making it a promising alternative to CMOS technology. However, the scalability of AQFP circuits is constrained by the large footprint of the transformer within AQFP cells and the limitations of AC clocking [2]. The Double Gate Process (DGP) [3] is a double-active-layer niobium fabrication process which provides the opportunity to construct more compact circuit designs without the need to alter established and verified cell layouts. We present AQFP logic circuits fabricated on both active layers of the DGP and present experimental results on their operating margins.

References
1. N. Takeuchi et al., SUST 26, no. 3, 035010 (2013).
2. S. K. Tolpygo, IEEE TAS 33, no. 2, 3230373 (2023)
3. T. Ando et al., SUST 30, no. 7, 075003 (2017).