Demonstration of a Hybrid AQFP-RSFQ 1-bit Microprocessor Datapath with Low-Latency Feedback
2025-06-17 , Room "Berlin & Oslo"

Superconducting integrated circuits offer a promising solution to the challenges faced by modern information infrastructure primarily based on CMOS technology. In particular, adiabatic quantum-flux-parametron (AQFP) circuits have garnered attention due to their superior energy efficiency compared to conventional integrated circuits. However, one of the challenges in AQFP is the limited interconnect length between adjacent logic gates (< 0.7 mm) due to the cumulative inductance that attenuates the data signal amplitude. Keeping interconnects short is necessary to maintain a low bit-error-rate during data signal propagation. To compensate for this limitation, additional buffer/booster gates used as repeaters are required to recover data signals. This approach introduces additional latency due to the fully synchronized nature of AQFP. To address this, we propose a low-latency pathway implemented using rapid single-flux-quantum (RSFQ) technology, along with interface circuits between AQFP and RSFQ logic, as an alternative to the conventional AQFP buffer/booster repeaters. In this presentation, we will report on the experimental demonstration of a 1-bit AQFP-RSFQ microprocessor datapath in which the feedback is implemented using RSFQ logic and corresponding interface circuits. The latency of the feedback path is reduced by 67% at 5GHz speed. Our results confirm that computed data can be successfully written back to the AQFP registers through the RSFQ datapath at 100kHz test.


Affiliation:

Department of Electrical and Computer Engineering, Yokohama National University, Japan

Additional Authors with Affiliation:

Christopher L. Ayala and Nobuyuki Yoshikawa, Institute of Advanced Sciences, Yokohama National University, Japan