Double side etched asymmetrical mechanically robust superconducting through-silicon vias for quantum processing unit
2025-06-19 , Room "Berlin & Oslo"

Growing the number of qubits inside a processor unit is a challenging task in development of quantum computer. 3D integration emerges as a crucial technology for the advancement and scalability of superconducting qubit-based processor, with through-silicon vias (TSVs) serving as a fundamental component in facilitating high-density interconnects. In this study, we introduce superconducting TSVs that eliminate the use of deposited amorphous dielectrics, which significantly reduces microwave loss and ensures seamless compatibility with high-fidelity qubits. Our innovative approach effectively addresses the critical challenges associated with the 3D integration of quantum processing units (QPUs), thereby enhancing both coherence and scalability.
We further advance TSV technology by substituting the traditionally fragile metallic membrane with a robust silicon-based layer. This modification not only improves mechanical stability but also increases chip yield, making it a more reliable option for manufacturing. The enhanced design strengthens the overall TSV structure and promotes the growth and patterning of additional functional layers, thereby extending the versatility of our integration platform. Our findings underscore that these superconducting TSVs offer a scalable solution for the next generation of quantum computing architectures, paving the way for more efficient and powerful quantum systems.

Acknowledgement: OpenSuperQPlus100 project


Affiliation:

VTT Technical Research Centre of Finland

Additional Authors with Affiliation:

Harshad Mishra, Jukka-Pekka Kaikkonen, Rishabh Upadhyay, Mikael Kervinen, Wisa Förbom, Marco Marin Suarez. (all co-authors are with VTT Technical Research Centre of Finland)