We present the design, simulations, and testing of a Josephson sampler circuit with electrical bandwidth exceeding 100 GHz and potential applications for digital SFQ circuits. We simulated sampler circuit designs consisting of a single, hysteretic (latching) Josephson junction (JJ) as the logical sampling element (comparator) and a Faris pulser circuit that provides a fast (< 2 ps) sampling “strobe” pulse; we explored the impacts on sampler performance due to the signal-comparator coupling scheme used (galvanic, inductive, or capacitive), with the goal of balancing the highest sampler bandwidth with the minimum amount of distortion in the sampled waveform. Using these simulation results, we designed and characterized a JJ sampler chip operating at 3.6 K and fabricated using niobium JJs with amorphous Si barriers (Nb/a-Si/Nb) and critical current density Jc = 0.22 mA/μm2. Our cryocooled, fully-digital, and automated sampling system has an acquisition time of ∼ 1 s per data point and uses a binary search algorithm for comparator threshold determination; the binary search is also implemented in simulations to allow direct comparison between the measured and simulated sampled waveforms. With this sampler, we measured a 10% to 90% rise time of 3.3 ps for SQUID-generated step signals and a full width at half maximum of 2.5 ps for impulses from a Faris pulser circuit; both circuits were located on-chip and galvanically connected to the input of the sampler comparator.